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philips semiconductors pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins product data supersedes data of 2002 sep 27 2003 sep 12 integrated circuits
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2 2003 sep 12 features ? 8 general purpose input/output expander/collector ? replacement for pcf8574 with integrated 2-kbit eeprom ? internal 256 8 eeprom ? self timed write cycle (5 ms typ) ? 16 byte page write operation ? i 2 c and smbus interface logic ? internal power-on reset ? noise filter on scl/sda inputs ? active low interrupt output ? 6 address pins allowing up to 64 devices on the i 2 c/smbus ? no glitch on power-up ? supports hot insertion ? power-up with all channels configured as inputs ? low standby current ? operating power supply voltage range of 2.5 v to 3.6 v ? 5 v tolerant inputs/outputs ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma ? packages offered: so20, tssop20, hvqfn20 description the pca9501 is an 8-bit i/o expander with an on-board 2-kbit eeprom. the i/o expandable eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as leds. the system master writes to the i/o configuration bits in the same way as for the pcf8574. the data for each input or output is kept in the corresponding input or output register. the system master can read all registers. the eeprom can be used to store error codes or board manufacturing data for read-back by application software for diagnostic purposes and are included in the i/o expander package. the pca9501 active-low open-drain interrupt output is activated when any input state differes from its corresponding input port register state. it is used to indicate to the system master that an input state has changed and the device needs to be interrogated. the pca9501 has six address pins with internal pull-up resistors allowing up to 64 devices to share the common two wire i 2 c software protocol serial data bus. the fixed gpio address starts with ?1? and the fixed eeprom i 2 c address starts with ?0?, so the pca9501 appears as two separate devices to the bus master. the pca9501 supports hot insertion to facilitate usage in removable cards on backplane systems. ordering information packages temperature range order code topside mark drawing number 20-pin plastic so -40 to +85 c pca9501d pca9501d sot163-1 20-pin plastic tssop -40 to +85 c pca9501pw pca9501 sot360-1 20-pin plastic hvqfn -40 to +85 c PCA9501BS 9501 sot662-1 standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. smbus as specified by the smart battery system implementers forum is a derivative of the philips i 2 c patent. i 2 c is a trademark of philips semiconductors corporation.
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 3 pin configuration - so, tssop sw00903 a0 a1 a2 i/o0 i/o3 v dd sda scl 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 i/o1 i/o2 int wc i/o7 i/o6 i/o5 i/o4 9 12 10 11 a5 v ss a3 a4 pca9501 figure 1. pin configuration - so, tssop pin configuration - hvqfn 15 14 13 12 11 6 7 8 9 10 1 2 3 4 5 20 19 18 17 16 sw02017 top view a2 i/o0 i/o1 i/o2 i/o3 int a5 v ss a4 a3 i/o4 i/o7 wc i/o5 i/o6 scl sda v dd a0 a1 figure 2. pin configuration - hvqfn pin description pin number symbol name and function so, tssop hvqfn 1, 2, 3, 9, 11, 12 19, 20, 1, 7, 9, 10 a0-5 address lines (internal pull-up) 4, 5, 6, 7 2, 3, 4, 5 i/o0-3 quasi-bidirectional i/o pins 8 6 int active low interrupt output (open drain) 10 8 v ss supply ground 13, 14, 15, 16 11, 12, 13, 14 i/o4-7 quasi-bidirectional i/o pins 17 15 wc active low write control pin 18 16 scl i 2 c serial clock 19 17 sda i 2 c serial data 20 18 v dd supply voltage
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 4 block diagram power-on reset input filter i 2 c/smbus control input/ output ports write pulse read pulse a0 a1 a2 scl sda v dd v ss 8-bit i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 sw01077 pca9501 wc eeprom 256 x 8 a3 a4 a5 300 k ? int v cc lp filter figure 3. block diagram
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 5 functional description sw00788 write pulse data from shift register power-on reset read pulse data to shift register v dd i/o0 to i/o7 v ss 100 a c i s dq ff c i s dq ff to interrupt logic figure 4. simplified schematic diagram of each i/o device addressing following a start condition the bus master must output the address of the slave it is accessing. the address of the pca9501 is shown in figure 5. internal pullup resistors are incorporated on the hardware selectable address pins. 0 a5 a4 a3 a2 a1 a0 a5 1a4a3a2a1a0 a. b. (a) i/o expander (b) memory sw02006 slave address slave address hardware programmable fixed fixed r/w r/w hardware programmable figure 5. pca9501 slave addresses the last bit of the address byte defines the operation to be performed. when set to logic 1 a read is selected while a logic 0 selects a write operation. control register the pca9501 contains a single 8-bit register called the control register, which can be written and read via the i 2 c bus. this register is sent after a successful acknowledgment of the slave address. it contains the i/o operation information.
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 6 i/o operations (see also figure 4) each of the pca9501 ? s eight i/os can be independently used as an input or output. output data is transmitted to the port by the i/o write mode (see figure 6). input i/o data is transferred from the port to the microcontroller by the read mode (see figure 7). s 0 a5 a4 a3 a2 a1 a0 0 a data 1 a data 2 a sda scl t pv 12345678 t pv data 2 valid data 1 valid sw00649 acknowledge from slave r/w start condition acknowledge from slave acknowledge from slave slave address (i/o expander) data to port data to port write to port data out from port figure 6. i/o write mode (output) s 0 a5 a4 a3 a2 a1 a0 1 a data 1 a data 4 1 sda t ph t ps data 4 p data 2 data 3 sw00650 slave address (i/o expander) data from port data from port read from port data into port start condition acknowledge from slave r/w acknowledge from master stop condition data 1 int t iv t ir figure 7. i/o read mode (input)
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 7 quasi-bidirectional i/os (see figure 8) a quasi-bidirectional i/o can be used as an input or output without the use of a control signal for data direction. at power-on the i/os are high. in this mode, only a current source to v dd is active. an additional strong pull-up to v dd allows fast rising edges into heavily loaded outputs. these devices turn on when an output is written high, and are switched off by the negative edge of scl. the i/os should be high before being used as inputs. s 0 a2 a1 a0 0 a a a sda scl 12345678 sw00904 acknowledge from slave r/w start condition acknowledge from slave slave address (i/o expander) data to port data to port 1 i/o3 0 i/o3 p i/o3 output voltage i/o3 pull-up output current i oht i oh a 5 a 4 a 3 figure 8. transient pull-up current i oht while i/o3 changes from low-to-high and back to low
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 8 interrupt (see figs 9 and 12) the pca9501 provides an open drain output (int ) which can be fed to a corresponding input of the microcontroller. this gives these chips a type of master function which can initiate an action elsewhere in the system. an interrupt is generated by any rising or falling edge of the port inputs in the input mode. after time t iv the signal int is valid. resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt. resetting occurs as follows: ? in the read mode at the acknowledge bit after the rising edge of the scl signal ? in the write mode at the acknowledge bit after the high-to-low transition of the scl signal ? returning of the port data to its original setting. ? interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. each change of the i/os after resetting will be detected and, after the next rising clock edge, will be transmitted as int . reading from or writing to another device does not affect the interrupt circuit. sw00790 pca9501 (1) int pca9501 (2) int pca9501 (16) int microcontroller int v dd figure 9. application of multiple pca9501s with interrupt s 0 a5 a4 a3 a2 a1 a0 1 a 1 1 sda scl 12 345 678 t ir sw00791 acknowledge from slave r/w start condition stop condition slave address (i/o expander) data from port data into i/o5 int p i/o5 t iv figure 10. interrupt generated by a change of input to i/o5
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 9 memory operations write operations write operations require an additional address field to indicate the memory address location to be written. the address field is eight bits long providing access to any one of the 256 words of memory. there are two types of write operations, byte write and page write. write operation is possible when wc control pin put at a low logic level (0). when this control signal is set at 1, write operation is not possible and data in the memory is protected. byte write and page write explained below assume that write control pin (wc ) is set to 0. byte write (see figure 11) to perform a byte write the start condition is followed by the memory slave address and the r/w bit set to 0. the pca9501 will respond with an acknowledge and then consider the next eight bits sent as the word address and the eight bits after the word address as the data. the pca9501 will issue an acknowledge after the receipt of both the word address and the data. to terminate the data transfer the master issues the stop condition, initiating the internal write cycle to the non-volatile memory. only write and read operations to the quasi-bidirectional i/os are allowed during the internal write cycle. page write (see figure 12) a page write is initiated in the same way as the byte write, if after sending the first word of data, the stop condition is not received the pca9501 considers subsequent words as data. after each data word the pca9501 responds with an acknowledge and the four least significant bits of the memory address field are incremented. should the master not send a stop condition after 16 data words the address counter will return to its initial value and overwrite the data previously written. after the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle. sw00651 s 1 a5 a4 a3 a2 a1 a0 0 a a sda acknowledge from slave r/w start condition acknowledge from slave slave address (memory) word address a p data acknowledge from slave stop condition. write to the memory is performed figure 11. byte write sw00652 acknowledge from slave s 1 a5 a4 a3 a2 a1 a0 0 a a a sda acknowledge from slave r/w start condition acknowledge from slave slave address (memory) word address data to memory data n a p data n + 3 stop condition. write to the memory is performed data to memory figure 12. page write
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 10 read operations pca9501 read operations are initiated in an identical manner to write operations with the exception that the memory slave address ? r/w bit is set to a one. there are three types of read operations; current address, random and sequential. current address read (see figure 13) the pca9501 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1. when the pca9501 receives its memory slave address with the r/w bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. the master ceases the transmission by issuing the stop condition after the eighth bit. there is no ninth clock cycle for the acknowledge. random read (see figure 14) the pca9501 ? s random read mode allows the address to be read from to be specified by the master. this is done by performing a dummy write to set the address counter to the location to be read. the master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the pca9501 the master reissues the start condition and memory slave address with the r/w bit set to one. the pca9501 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. the master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. sequential read (see figure 15) the pca9501 sequential read is an extension of either the current address read or random read. if the master doesn ? t issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the pca9501 will increment the address counter and use the next eight cycles to transmit the data from that location. the master can continue this process to read the contents of the entire memory. upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. the master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge. sw00653 s 1 a5 a4 a3 a2 a1 a0 1 a sda acknowledge from slave r/w start condition slave address (memory) data from memory p stop condition figure 13. current address read sw00654 s p sda 1 a5a4a3a2a1a0 a a 0 start condition r/w acknowledge from slave acknowledge from slave a acknowledge from slave data from memory stop condition s start condition 1a5 a4a3a2a1a0 1 r/w slave address (memory) word address slave address (memory) figure 14. random read sw00655 s p sda slave address (memory) data from memory data from memory 1a5a4a3a2a1a0 a a 1 start condition r/w acknowledge from slave acknowledge from master data n a acknowledge from master data n+x stop condition data n+1 data from memory figure 15. sequential read
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 11 characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer one data bit is transferred during each clock phase. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 16). start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 17). system configuration a device generating a message is a ? transmitter ? , a device receiving is the ? receiver ? . the device that controls the message is the ? master ? and the devices which are controlled by the master are the ? slaves ? (see figure 18). sda scl sw00542 data line stable; data valid change of data allowed figure 16. bit transfer sda scl p sda scl s sw00543 start condition stop condition figure 17. definition of start and stop conditions sda scl sw00544 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver figure 18. system configuration
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 12 acknowledge (see figure 19) the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse, set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. s 9 8 2 1 sw00545 data output by transmitter data output by receiver scl from master acknowledge not acknowledge clock pulse for acknowledgement start condition figure 19. acknowledgment on the i 2 c-bus
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 13 typical application applications ? board version tracking and configuration ? board health monitoring and status reporting ? multi-card systems in telecom, networking, and base station infrastructure equipment ? field recall and troubleshooting functions for installed boards ? general-purpose integrated i/o with memory ? replacement for pcf8574 with integrated 2-kbit eeprom ? bus master sees gpio and eeprom as two separate devices ? six hardware address pins allow up to 64 pca9501s to be located in the same i 2 c/smbus control eeprom gpio i 2 c i 2 c i 2 c i 2 c asic backplane cpu or c i 2 c monitoring and control inputs alarm leds pca9501 card id, subroutines, configuration data, or revision history sw02007 up to 64 cards configuration control i 2 c figure 20. typical application a central processor/controller typically located on the system main board can use the 400 khz i 2 c/smbus to poll the pca9501 devices located on the system cards for status or version control type of information. the pca9501 may be programmed at manufacturing to store information regarding board build, firmware version, manufacturer identification, configuration option data alternately, these devices can be used as convenient interface for board configuration, thereby utilizing the i 2 c/smbus as an intra-system communication bus.
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 14 typical application sw01078 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 v dd v dd scl sda int int reset master controller gnd scl sda pca9501 a2 a1 a0 v ss v dd subsystem 3 (e.g. alarm system) subsystem 2 (e.g. counter) subsystem 1 (e.g. temp sensor) int v dd alarm controlled switch (e.g. cbt device) enable 1.6 k ? 1.6 k ? 1.1 k ? 2 k ? note: gpio device address configured as 0110000 for this example eeprom device address configured as 1110000 for this example i/0 0 , i/0 2 , i/0 3 , configured as outputs i/0 1 , i/0 4 , i/0 5 , configured as inputs i/0 06 , i/0 7 , are not used and have to be configured as outputs a b 2 k ? a3 a4 a5 (optional) figure 21. typical application
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 15 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied. symbol parameter min max unit v cc supply voltage -0.5 4.0 v v i input voltage v ss - 0.5 5.5 v i i dc input current -20 20 ma i o dc output current -25 25 ma i dd supply current -100 100 ma i ss supply current -100 100 ma p tot total power dissipation ? 400 mw p o total power dissipation per output ? 100 mw t stg storage temperature -65 +150 c t amb operating temperature -40 +85 c dc electrical characteristics t amb = -40 c to +85 c unless otherwise specified; v cc = 3.3 v symbol parameter min typ max unit supply v dd supply voltage 2.5 3.3 3.6 v i ddq standby current; a 0 thru a 5 , wc = high ? ? 60 a i dd1 supply current read ? ? 1 ma i dd2 supply current write ? ? 2 ma v por power on reset voltage ? ? 2.4 v input scl; input, output sda v il input low voltage -0.5 ? 0.3 v dd v v ih input high voltage 0.7 v dd ? 5.5 v i ol output low current @ v ol = 0.4 v 3 ? ? ma i l input leakage current @ v i = v dd or v ss -1 ? 1 a c i input capacitance @ v i = v ss ? ? 7 pf i/o expander port v il input low voltage -0.5 ? 0.3 v dd v v ih input high voltage 0.7 v dd ? 5.5 v i ihl(max) input current through protection diodes -400 ? 400 a i ol output low current @ v ol = 1 v 10 25 ? ma i oh output high current @ v oh = v ss 30 100 300 a i oht transient pull-up current ? 2 ? ma c i input capacitance ? ? 10 pf c o output capacitance ? ? 10 pf address inputs a 0 thru a 5 , wc input v il input low voltage -0.5 ? 0.3 v dd v v ih input high voltage 0.7 v dd ? 5.5 v i l input leakage current @ v i = v dd -1 ? 1 a l input leakage (pull-up) current @ v i = v ss 10 25 100 a interrupt output int i ol low level output current; v ol = 0.4 v 1.6 ? ? ma i l leakage current @ v i = v dd or v ss -1 ? +1 a
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 16 non-volatile storage specifications parameter specification memory cell data retention 10 years minimum number of memory cell write cycles 100,000 cycles minimum i 2 c-bus timing characteristics symbol parameter min. typ. max. unit i 2 c-bus timing (see figure 22; note 1) f scl scl clock frequency ? ? 400 khz t sw tolerable spike width on bus ? ? 50 ns t buf bus free time 1.3 ? ? s t su;sta start condition set-up time 0.6 ? ? s t hd;sta start condition hold time 0.6 ? ? s t r scl and sda rise time ? ? 0.3 s t f scl and sda fall time ? ? 0.3 s t su;dat data set-up time 250 ? ? ns t hd;dat data hold time 0 ? ? ns t vd;dat scl low to data out valid ? ? 1.0 s t su;sto stop condition set-up time 0.6 ? ? s note: 1. all the timing values are valid within the operating supply voltage and ambient temperature range and refer to v il and v ih with an input voltage swing of v ss to v dd . port timing characteristics symbol parameter min typ max unit t pv output data valid; c l 100 pf ? ? 4 s t ps input data setup time; c l 100 pf 0 ? ? s t ph input data hold time; c l 100 pf 4 ? ? s t iv interrupt input data valid time; c l 100 pf ? ? 4 s t ir interrupt reset time; c l 100 pf ? ? 4 s
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 17 handbook, full pagewidth scl sda mbd820 bit 0 lsb (r/w) t hd;sta t su;dat t hd;dat t vd;dat t su;sto t f r t t buf t su;sta 1 / f scl start condition (s) bit 7 msb (a7) bit 6 (a6) acknowledge (a) stop condition (p) sw00561 protocol figure 22. power-up timing symbol parameter max. unit t pur 1 power-up to read operation 1 ms t puw 1 power-up to write operation 5 ms note: 1. t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are guaranteed by design. write cycle limits symbol parameter min. typ. (5) max. unit t wr 1 write cycle time ? 5 10 ms note: 1. t wr is the maximum time that the device requires to perform the internal write operation. write cycle timing scl sda 8th bit word n ack stop condition start condition memory address t wr sw00560 figure 23.
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 18 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). dip soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. so and ssop reflow soldering reflow soldering techniques are suitable for all so and ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: ? a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. ? the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 19 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 20 hvqfn20: plastic, heatsink very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm sot662-1
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 21 revision history rev date description _2 20030912 product data (9397 750 12058); ecn 853-2370 30128 dated 18 july 2003. supersedes data of 2002 september 27 (9397 750 10327). modifications: ? addition of hvqfn package type. _1 2002 sep 27 product data (9397 750 10327); initial version engineering change notice: 853-2370 28875 (2002 sep 09)
philips semiconductors product data pca9501 8-bit i 2 c and smbus i/o port with interrupt, 2-kbit eeprom and 6 address pins 2003 sep 12 22 purchase of philips i 2 c components conveys a license under the philips ? i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products ? including circuits, standard cells, and/or software ? described or contained herein in order to improve design and/or performance. when the product is in full production (status ? production ? ), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 09-03 document order number: 9397 750 12058 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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